The present invention relates to memories generally and, more particularly, to circuits, architectures, and methods for generating a periodic signal in a memory.
First-In First-Out (FIFO) memories are used to provide a temporary buffer or storage between two communication devices running asynchronously. In FIFOs with bus matching capabilities, data can be written to and read from the FIFO in different data sizes and frequencies, depending on a particular bus mode of operation. For example, a 36-bit wide data word can be delivered in the form of a byte (i.e., x9), a word (i.e., x18) or a long word (x36) bus mode. Referring to FIG. 1a, a byte 10, a word 12 and a long word 14 are shown. The byte 10 is shown having bits from 0 to 8. The word 12 is shown having bits from 0 to 17. The long word 14 is shown having bits from 0 to 35.
Referring to FIG. 1b, a FIFO 16 is shown receiving a number of long words 14a-14n and presenting a number of bytes 10a-10n, a number of words 12a-12n and a long word 14i. The number of bytes 10a-10n, the number of words 12a-12n and the long word 14i are shown grouped so that a x36 FIFO is implemented. The FIFO 16 has an output 18 that presents status flags indicating the various parameters (i.e., fullness or emptiness) of the FIFO 16. The FIFO 16 also has an input 20 that receives a control signal BM and a second control signal SIZE that control the bus matching and bus sizing, respectively.
FIFOs often have write flag counters and read flag counters to keep track of the number of long words written to (i.e., loaded) and read from (i.e., unloaded) the FIFO. The flag counter must therefore be synchronized with the particular bus mode. In particular, the flag counter should only be incremented when an entire 36-bit operation is finished loading or unloading. The flag counter should increment (i) every cycle if the data packet is in long word form, (ii) every 2 cycles if the data packet is in word form and (iii) every 4 cycles if the data packet is in byte form.
One conventional approach to implementing the flag counter incrementer would be to use a divide-by-2 and a divide-by-4 flag counter, depending on the particular bus mode. However, such an implementation would have the disadvantage of having a slow operation time and/or consume a large amount of chip area. FIG. 2 shows a circuit 30 illustrating such an approach.
Another conventional approach to implementing the flag counter incrementer would be to use a state machine to re-generate a flag bus-matching clock. However, such an implementation would have the disadvantage of having a slow operation time. FIG. 3 shows a circuit 40 illustrating such an approach.
The present invention concerns a circuit comprising a clock generator and a state machine. The clock generator may be configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal. The state machine may be configured to generate the second enable signal in response to a first and a second control signal.
The objects, features and advantages of the present invention include providing a flag counter incrementer that may adapt to a particular bus mode that may (i) have a fast operation time; (ii) consume a minimum amount of chip area; (iii) allow dynamic bus-matching re-configuration during operation without requiring a master reset of the FIFO; and/or (iv) transceive a data stream in the form of byte (e.g., 9 bit), word (e.g., 18 bit) or long word (e.g., 36 bit).